In theory, synchronous clock multiplication is an easy task. A simple PLL with two digital dividers—one inserted just after the VCO (voltage-controlled oscillator) and the second one placed directly ...

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

There are three popular clock distribution architectures used to facilitate communication between ICs in a circuit board: common clock, embedded clock and source synchronous clock. In the common clock ...

Timing relationships between signals are critical to reliable operation of digital designs. With synchronous designs, the timing of the clock signal relative to data signals is especially important.